4432-T-B1 B 915【PDF 33/47 页】KIT DEV TEST EZRADIOPRO SI4432

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Si4430/31/32-B1

Rev 1.1

4.2. Modulation Data Source

The Si4430/31/32 may be configured to obtain its modulation data from one of three different sources: FIFO mode,

Direct Mode, and from a PN9 mode. In Direct Mode, the TX modulation data may be obtained from several

different input pins. These options are set through the dtmod[1:0] field in "Register 71h. Modulation Mode Control

2".

4.2.1. FIFO Mode

In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The FIFOs are

accessed via "Register 7Fh. FIFO Access," and are most efficiently accessed with burst read/write operation as

discussed in "3.1. Serial Peripheral Interface (SPI)" on page 18.

In TX mode, the data bytes stored in FIFO memory are "packaged" together with other fields and bytes of

information to construct the final transmit packet structure. These other potential fields include the Preamble, Sync

word, Header, CRC checksum, etc. The configuration of the packet structure in TX mode is determined by the

Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler Registers (see Table 13 on

page 45). If the Automatic Packet Handler is disabled, the entire desired packet structure should be loaded into

FIFO memory; no other fields (such as Preamble or Sync word are automatically added to the bytes stored in FIFO

memory). For further information on the configuration of the FIFOs for a specific application or packet size, see "6.

Data Handling and Packet Handler" on page 41.

In RX mode, only the bytes of the received packet structure that are considered to be "data bytes" are stored in

FIFO memory. Which bytes of the received packet are considered "data bytes" is determined by the Automatic

Packet Handler (if enabled), in conjunction with the Packet Handler Registers (see Table 13 on page 45). If the

Automatic Packet Handler is disabled, all bytes following the Sync word are considered data bytes and are stored

in FIFO memory. Thus, even if Automatic Packet Handling operation is not desired, the preamble detection

threshold and Sync word still need to be programmed so that the RX Modem knows when to start filling data into

the FIFO. When the FIFO is being used in RX mode, all of the received data may still be observed directly (in real-

time) by properly programming a GPIO pin as the RXDATA output pin; this can be quite useful during application

development.

When in FIFO mode, the chip will automatically exit the TX or RX State when either the ipksent or ipkvalid interrupt

occurs. The chip will return to the IDLE mode state programmed in "Register 07h. Operating Mode and Function

Control 1". For example, the chip may be placed into TX mode by setting the txon bit, but with the pllon bit

additionally set. The chip will transmit all of the contents of the FIFO and the ipksent interrupt will occur. When this

interrupt event occurs, the chip will clear the txon bit and return to TUNE mode, as indicated by the set state of the

pllon bit. If no other bits are additionally set in register 07h (besides txon initially), then the chip will return to the

STANDBY state.

In RX mode, the rxon bit will be cleared if ipkvalid occurs and the rxmpk bit (RX Multi-Packet bit, SPI Register 08h

bit [4]) is not set. When the rxmpk bit is set, the part will not exit the RX state after successfully receiving a packet,

but will remain in RX mode. The microcontroller will need to decide on the appropriate subsequent action,

depending upon information such as an interrupt generated by CRC, packet valid, or preamble detect.

Add R/W Function/Description

POR Def.

71 R/W

Modulation Mode

Control 2

trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0]

00h

dtmod[1:0]

Data Source

Direct Mode using TX/RX Data via GPIO pin (GPIO configuration required)

Direct Mode using TX/RX Data via SDI pin (only when nSEL is high)

FIFO Mode

PN9 (internally generated)

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